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preliminary quad pll programmable clock generator with spread spectrum cy2546 cy2544 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-12563 rev. *a revised february 28, 2007 features ? four fully integrated phase-locked loops (plls) ? input frequency range: ? external crystal: 8 to 48 mhz ? external reference: 8 to 166 mhz clock ? wide operating output frequency range ? 3 to 166 mhz ? programmable spread spectrum with center and down spread option and lexmark modulation profile ? two vdd core voltage options: ? 2.5v, 3.0v, and 3.3v for cy2544 ? 1.8v for cy2546 ? selectable output voltages: ? 2.5v, 3.0v, and 3.3v for cy2544 ? 1.8v for cy2546 ? frequency select feature with op tion to select eight different frequencies ? low jitter, high accuracy outputs ? up to nine clock outputs ? programmable output drive strength ? glitch-free outputs while frequency switching ? 24-pin qfn package ? commercial and industrial temperature ranges benefits ? multiple high-performance plls allow synthesis of unrelated frequencies ? nonvolatile programming for customized pll frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ? two spread spectrum capable plls with linear or lexmark profile for maximum emi reduction ? spread spectrum plls can be disabled or enabled separately ? plls can be programmed fo r system frequency margin tests ? meets critical timing requ irements in complex system designs ? suitable for pc, consumer, and networking applications ? ability to synthesize standard frequencies with ease ? application compatibility in standard and low-power systems block diagram osc mux and control logic pll1 pll2 pll3 (ss) pll4 (ss) output dividers and drive strength control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 4of6 crossbar switch exclkin fs2 fs1 fs0 sson xout xin pd#/oe bank 1 bank 3 bank 2
preliminary cy2546 document #: 001-12563 rev. *a page 2 of 11 cy2544 pin configuration e x c l k i n clk1 pd#oe cy2544 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 nc clk2 p d # / o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b2 clk7/sson vdd_clk_b3 clk8 gnd clk9 v d d x o u t x i n g n d 24ld qfn e x c l k i n clk1 pd#oe cy2546 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 vdd_core clk2 p d # / o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b2 clk7/sson vdd_clk_b3 clk8 gnd clk9 v d d _ c o r e x o u t x i n g n d 24ld qfn pin description - cy2544 (2.5v, 3.0v or 3.3v vdd) pin number name i/o description 1 gnd power power supply ground for core 2 clk1 output programmable output clock 3 vdd_clk_b1 power 2.5v/3.0v/3.3v power supply for output bank1 (clk1, clk2, clk3) output 4 pd#/oe input power down or output enable 5 nc nc no connect 6 clk2 output programmable output clock 7 gnd power power supply ground for output bank 1 8 clk3/fs0 output/input multifunction progra mmable pin,clk3 output clock or frequency select pin fs0 9 pd#/oe/fs1 input multifunction programmable pin, power down, output enable or frequency select pin fs1 10 clk4/fs2 output/input multifunction programmable pin, cl k4 output or frequency select input pin fs2 11 clk5 output programmable output clock 12 gnd power power supply ground for output bank 2 13 clk6 output programmable output clock 14 vdd_clk_b2 power 2.5v/3.0v/3.3v power supply for output bank2 (clk4, clk5, clk6) output 15 clk7/sson output/input multifunction programmable pin, clk7 output or sson input 16 vdd_clk_b3 power 2.5v/3.0v/3.3v power supply for output bank3 (clk7, clk8, clk9) output 17 clk8 output programmable output clock 18 gnd power power supply ground for output bank 3
preliminary cy2546 document #: 001-12563 rev. *a page 3 of 11 cy2544 19 gnd power power supply ground for core 20 clk9 output programmable output clock 21 exclkin input external clock input 22 vdd power 2.5v/3.0v/3.3v power supply 23 xout output crystal output 24 xin input crystal input pin description - cy2544 (2.5v, 3.0v or 3.3v vdd) (continued) pin number name i/o description pin description - cy2546 (1.8v vdd_core) pin number name i/o description 1 gnd power power supply ground for core 2 clk1 output programmable output clock 3 vdd_clk_b1 power 1.8v power supply for output bank1 (clk1, clk2, clk3) output 4 pd#/oe input power down or output enable 5 vdd_core power supply 1.8v power supply for core 6 clk2 output programmable output clock 7 gnd power power supply ground for output bank 1 8 clk3/fs0 output/input multifunction programmable pin,clk3 output clock or frequency select pin fs0 9 pd#/oe/fs1 input multifunction programmable pin, power down, output enable or frequency select pin fs1 10 clk4/fs2 output/input multifunction programmable pin, clk4 output or frequency select input pin fs2 11 clk5 output programmable output clock 12 gnd power power supply ground for output bank 2 13 clk6 output programmable output clock 14 vdd_clk_b2 power 1.8v power supply for output bank2 (clk4, clk5, clk6) output 15 clk7/sson output/input multifunction programmable pin, clk4 output or sson input 16 vdd_clk_b3 power 1.8v power supply for output bank3 (clk7, clk8, clk9) output 17 clk8 output programmable output clock 18 gnd power power supply ground for output bank 3 19 gnd power power supply ground for core 20 clk9 output programmable output clock 21 exclkin input external low voltage reference clock input 22 vdd_core power 1.8v power su pply for core 23 xout output crystal output 24 xin input crystal input
preliminary cy2546 document #: 001-12563 rev. *a page 4 of 11 cy2544 general description the cy2544 and cy2546 are four-pll programmable spread spectrum clock generators used to reduce emi found in high-speed digital electronic systems. two of the four plls have spread spectrum capability. the spread spectrum feature is turned on or off using the control pin sson. the advantage of having four plls is that a single device can generate up to four independent families of frequencies from a single crystal or reference input frequency. generally, a design requires up to four oscillators to achieve the same result as a single cy2544 or cy2546. the device uses cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the input clock. frequency modulating the clock greatly reduces the measured emi at the fundamental and harmonic frequencies. this reduction in radiated energy significantly reduces the cost of complying with regulatory agency (emc) requirements and improves time-to-market without degrading t he system performance. the cy2544 and cy2546 use a factory/field-programmable configuration memory array to provide customization for output frequencies, frequency se lect options, spread charac- teristics like spread percentage and modulation frequency, output drive strength and crystal load capacitance. customized devices are configured using cyberclocks? software or by contacting the factory. the spread percentage is programmed to either center spread or down spread with various spread percentages. the range for center spread is from 0.125% to 2.50%. the range for down spread is from ?0.25% to ?5.0%. contact the factory for smaller or larger spread percentage amounts, if required. the input to the cy2544 and cy2546 is either a crystal or a clock signal. the input frequency range for crystals is 8 mhz to 48 mhz, and for clock signals is 8 mhz to 166 mhz. in addition, there is a separate input for a clock reference. the cy2544 and cy2546 have nine clock outputs and each output has four possible input sources. there are three frequency select lines fs(2:0) that provide an option to select eight different sets of frequ encies among each of the four plls. each output has programmable output divider options. output 1 has eight possible divider values and outputs 2?9 have four possible divider values for maximum flexibility. the 2-bit or 3-bit output dividers are programmable, providing a wide output frequency range. the outputs are glitch-free when frequency is switched using output dividers. the outputs can have a predictable phase relationship, if the clock source is the same pll and divider values are 2, 3, 4, or 6. the output banking feature allows the three sets of frequencies to operate at three different voltages. selectable output voltage options are 2.5v , 3.0v, or 3.3v for cy2544 and 1.8v for cy2546 part. the cy2544 and cy2546 are available in 24-pin qfn packages with commercial and industrial operating temper- ature ranges. table 1. supply voltage options device v dd supply voltage cy2544 cy2546 2.5v, 3.0v or 3.3v 1.8v
preliminary cy2546 document #: 001-12563 rev. *a page 5 of 11 cy2544 absolute maximum conditions parameter description condition min. max. unit v dd supply voltage for cy2544 ?0.5 4.5 v v dd_core supply voltage for cy2546 ?0.5 2.6 v v dd_clk_bx supply voltage for cy2544 ?0.5 4.5 v supply voltage for cy2546 ?0.5 2.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? volts ul-94 flammability rating @1/8 in. v-0 msl moisture sensitivity level qfn package 3 recommended operating conditions parameter descripti on min. typ. max. unit v dd vdd operating at 3.3v for cy2544 3.00 ? 3.60 v v dd vdd operating at 3.0v for cy2544 2.70 ? 3.30 v v dd vdd operating at 2.5v for cy2544 2.25 ? 2.75 v v dd_core vdd_core operating at 1.8v for cy2546 1.65 ? 1.95 v v dd_clk_bx output driver voltage for bank 1, 2 an d 3 operating at 3.3v (cy2544) 3.00 ? 3.60 v v dd_clk_bx output driver voltage for bank 1, 2 an d 3 operating at 3.0v (cy2544) 2.70 ? 3.30 v v dd_clk_bx output driver voltage for bank 1, 2 an d 3 operating at 2.5v (cy2544) 2.25 ? 2.75 v v dd_clk_bx output driver voltage for bank 1, 2 an d 3 operating at 1.8v (cy2546) 1.65 ? 1.95 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 ? +85 c c load maximum load capacitance ? ? 15 pf t pu power-up time for all v dd pins to reach minimum specif ied voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter description conditions min. typ. max. unit v ol output low voltage, all clk pins all v dd levels, i ol = 8 ma ? ? 0.4 v v oh output high voltage, all clk pins all v dd levels, i oh = ?8 ma v dd ? 0.4 ? ? v v il all inputs except xin all v dd levels ?0.3 ? 0.2 * v dd v v ih all inputs except xin all v dd levels 0.8 * v dd ?v dd + 0.3 v v ilx input low voltage, clock input to xin pin all v dd levels ?0.3 ? 0.36 v v ihx input high voltage, clock input to xin pin all v dd levels 1.44 ? 2.0 v i ilpdoe input low current, pd#/oe and fs0,1,2 pins v in = v ss (no internal pull up) ? ? 1 a i ihpdoe input high current, pd#/oe and fs0,1,2 pins v in = v dd (no internal pull up) ? ? 1 a i ilsr input low current, sson pin v in = v ss (internal pull down = 160k typical) ??1 a i ihsr input high current, sson pin v in = v dd (internal pull down = 160k typical) ??25 a i dd [1] supply current all clocks running, no load ?15?ma i dds standby current all output power down ?50? a c in input capacitance - all inputs except xin sson, oe, pd# or fs inputs ??7pf
preliminary cy2546 document #: 001-12563 rev. *a page 6 of 11 cy2544 note 1. configuration dependent. ac electrical specifications parameter description conditions min. typ. max. unit f in (crystal) crystal frequency 8 ? 48 mhz f in (clock) input clock frequency (xin or exclkin) 8 ? 166 mhz f out output clock frequency 3 ? 166 mhz dc output duty cycle all clocks except ref out duty cycle is defined in figure 2, "duty cycle definition," on page 8 ; t 1 /t 2 , 50% of v dd 45 50 55 % dc ref out duty cycle ref in min 45%, max 55% 40 60 % e r clk1-9 rising edge rate v dd = all, 20% to 80% v dd 0.8 ? ? v/ns e f clk1-9 falling edge rate v dd = all, 20% to 80% v dd 0.8 ? ? v/ns t ccj1 cycle-to-cycle jitter configuration dependent. see ta b l e 2 , ?configuration example for jitter,? on page 6 ???ps t ltj long term jitter (1000 cycle period jitter) configuration dependent. see ta b l e 2 , ?configuration example for jitter,? on page 6 ???ns t 10 pll lock time ? 1 3 ms table 2. configuration example for jitter reference description max jitter (ps) on output 1(48mhz) max jitter (ps) on output 2 (27 mhz) max jitter (ps) on output 3 (166 mhz) max jitter (ps) on output 4 (74.25 mhz) cycle-to-cycle jitter 27mhz t ccj1 155 255 170 195 48 mhz t ccj1 135 225 100 125 long term jitter 27mhz t ltj 770 580 630 1105 48 mhz t ltj 535 575 520 795
preliminary cy2546 document #: 001-12563 rev. *a page 7 of 11 cy2544 recommended crystal specification for smd package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 28 mhz fmax maximum frequency 14 28 48 mhz r1(max) maximum motional resistance (esr) 135 50 30 c0(max) maximum shunt capacitance 4 4 2 pf cl(max) maximum parallel load capacitance 18 14 12 pf dl(max) maximum crystal drive level 300 300 300 w recommended crystal specification for thru-hole package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 24 mhz fmax maximum frequency 14 24 32 mhz r1(max) maximum motional resistance (esr) 90 50 30 c0(max) maximum shunt capacitance 7 7 7 pf cl(max) maximum parallel load capacitance 18 12 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w
preliminary cy2546 document #: 001-12563 rev. *a page 8 of 11 cy2544 test and measurement setup figure 1. test and measurement setup voltage and timing definitions figure 2. duty cycle definition figure 3. er = (0.6 x v dd ) /t 3 , ef = (0.6 x v dd ) /t 4 0.1 f v dds outputs c load gnd dut clock output v dd 50% of v dd 0v t 1 t 2 clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v
preliminary cy2546 document #: 001-12563 rev. *a page 9 of 11 cy2544 note 2. xxx indicates factory programmable are factory programmed config urations. for more details, cont act your local cypress fae or cypress sales representative. f in the part number indicates field pr ogrammable using cyberclocks online software. ordering information part number [2] type vdd(v) temperature range lead-free cy2544cxxx 24-pin qfn 3.3, 3.0 or 2.5 commercial, 0c to 70c cy2544cxxxt 24-pin qfn -tape & reel 3.3, 3.0 or 2.5 commercial, 0c to 70c cy2544fc 24-pin qfn 3.3, 3.0 or 2.5 commercial, 0c to 70c cy2544fct 24-pin qfn - tape & reel 3.3, 3.0 or 2.5 commercial, 0c to 70c cy2546cxxx 24-pin qfn 1.8 commercial, 0c to 70c cy2546cxxxt 24-pin qfn -t ape & reel 1.8 commercial, 0c to 70c cy2546fc 24-pin qfn 1.8 commercial, 0c to 70c cy2546fct 24-pin qfn -tape & reel 1.8 commercial, 0c to 70c cy2544ixxxt 24-pin qfn -tape & reel 3.3, 3.0 or 2.5 indus trial, -40c to +85c CY2544FI 24-pin qfn 3.3, 3.0 or 2.5 industrial, -40c to +85c CY2544FIt 24-pin qfn - tape & reel 3.3, 3.0 or 2.5 industrial, -40c to +85c cy2546ixxx 24-pin qfn 1.8 industrial, -40c to +85c cy2546ixxxt 24-pin qfn -tap e & reel 1.8 industria l, -40c to +85c cy2546fi 24-pin qfn 1.8 industrial, -40c to +85c cy2546fit 24-pin qfn -tape & reel 1.8 industrial, -40c to +85c
preliminary cy2546 cy2544 document #: 001-12563 rev. *a page 10 of 11 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions cyberclocks is a trademark of cypress semi conductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. figure 4. 24-lead qfn 4x4 mm (subcon punch type pkg with 2.49x2.49 epad) lf24a 5. package code ly24a lf24a part # description lead free standard 2. reference jedec#: mo-220 4. all dimensions are in mm [min/max] 1. hatch is solderable exposed metal. 3. package weight: 0.042g notes: solderable exposed pad c 1.00 max. n seating plane n 2 2 0.230.05 0.50 1 1 0.05 0-12 0.30-0.50 2.45 0.05 max. c 0.80 max. 0.20 ref. pin1 id 0.45 0.20 r. side view 3.90 4.10 3.70 3.80 4.10 3.70 3.80 3.90 0.420.18 2.55 2.55 2.45 (4x) top view bottom view 2.49 2.49 ?0.50 51-85203-*a
preliminary cy2546 document #: 001-12563 rev. *a page 11 of 11 cy2544 document history page document title: cy2544/cy2546 quad pll progra mmable clock generator with spread spectrum document number: 001-12563 rev. ecn no. issue date orig. of change description of change ** 690257 see ecn rgl new data sheet *a 790516 see ecn rgl separated the pin configuration drawing into two to show the difference between cy2544 and cy2546 pin outs. changed the idd from 22ma maximum to 25ma typical changed i ilsr internal pull down from 100k to 160k changed i ihsr internal pull down from 100k to 160k and changed the maximum value from 10 a to 25 a changed i ilpdoe to no internal pull up and changed the maximum value from 10 a to 1 a changed i ihpdoe to no internal pull up

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